Intel Unveils ZAM Memory Prototype with Z-Angle Architecture – What It Means for AI and Data Centers

Intel has officially introduced a prototype of its new memory technology called Z-Angle Memory, or ZAM. The announcement was made during the Intel Connection Japan 2026 event. This marks the first time the company has publicly demonstrated a working version of the technology. ZAM is being developed in partnership with Saimemory, a subsidiary of SoftBank, and it aims to challenge current High Bandwidth Memory (HBM) solutions.

Although Intel stepped away from the DRAM business many years ago, this new project shows that the company is exploring fresh opportunities in the memory market. The main goal of ZAM is to overcome thermal and performance limits that affect existing memory technologies, especially in high-performance computing and artificial intelligence workloads.

Intel Unveils ZAM Memory Prototype with Z-Angle Architecture — What It Means for AI and Data Centers

The key feature of ZAM is its unique “Z-Angle” architecture. In traditional stacked memory designs like HBM, vertical interconnects are drilled straight down through the layers of memory chips. These vertical pathways, often called through-silicon vias (TSVs), connect the stacked dies. While effective, this design can create heat concentration and limit efficiency as performance demands increase.

ZAM takes a different approach. Instead of routing connections vertically, the Z-Angle architecture uses staggered interconnects placed diagonally across the memory stack. This diagonal layout helps distribute heat more evenly throughout the structure. By reducing thermal hotspots, the memory can operate more efficiently and potentially at higher performance levels without overheating.

Intel claims that this new design could lower power consumption by 40 to 50 percent compared to current solutions. Reduced power usage is important not only for energy savings but also for managing heat in data centers and AI servers. As computing systems become more powerful, controlling heat and energy use becomes a major engineering challenge.

Another claimed benefit of ZAM is simplified manufacturing. The diagonal interconnect design may reduce some of the complexity involved in stacking and connecting multiple memory dies. If manucturing becomes easier and more scalable, production costs could decrease over time. This would make the technology more attractive to large-scale customers.

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ZAM is also expected to offer higher storage capacity per chip. Early information suggests that a single ZAM stack could support up to 512 GB. Higher density is particularly valuable for AI training and data-heavy applications, where large memory pools are required to handle complex models and massive datasets.

During the event, several senior Intel executives were present, including Joshua Fryman, Fellow and CTO of Intel Government Technologies, and Makoto Onho, CEO of Intel Japan. Their participation signals that Intel considers this project strategically important. While Intel’s exact technical role in the development has not been fully detailed, the company is said to be responsible for initial investment and key strategic decisions.

The ZAM prototype is still in its early stages, and it will take time before the technology reaches commercial production. However, its introduction suggests that Intel is serious about re-entering the advanced memory space. If the performance and thermal improvements meet expectations, ZAM could become a strong competitor in the high-bandwidth memory market and help support the next wave of AI-driven computing.